A 42-Gb/s Decision Circuit in 0.13µm CMOS
نویسندگان
چکیده
In this paper, a decision circuit based on 0.13μm CMOS is presented. It is designed for 40-Gb/s optical communication systems. This decision circuit achieved by master-slave flip-flops (MS-FFs) with opposite clock can operate at a bit rate of 40-Gb/s and beyond. Current-mode logic (CML) is adopted due to the higher speed compared to static CMOS and the robustness against common-mode disturbances. A 3stage output buffer is employed to drive the external 50Ω loads. On-chip shunt peaking (SP) inductors and split-resistor (SR) loads are used to boost the bandwidth. The decision circuit uses a single 1.2V supply and consumes a total current of 33mA. And the chip area is only 0.63mm with bonding pads.
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تاریخ انتشار 2008